Specifications

Technical reference.

Architecture and performance data for all three processor generations. All numbers from hardware measurements, not simulation.

N1

Loihi 1-class Production

Cores	128
Neurons per core	1,024
Synapses per core	131,072
Total synapses	16,777,216
Neuron model	LIF (leaky integrate-and-fire)
Spike format	Binary (1-bit)
Weight precision	16-bit signed
Membrane precision	16-bit signed
Leak model	Configurable decay constant
Refractory period	Programmable (0-63 timesteps)
Learning rule	STDP (spike-timing dependent plasticity)
On-chip memory	8 KB SRAM (neuron state + synaptic)
Clock frequency	62.5 MHz (FPGA)
Interface	AXI4-Lite register map
Target FPGA	Xilinx UltraScale+ (AWS F2)
LUT utilization	~12,000 (AWS F2)
BRAM utilization	~8 blocks
Test coverage	96 tests, all passing
FPGA validation	AWS F2: PASS, 62.5 MHz
Kria K26 (2-core)	20,109 LUTs (17.2%), 0.642W, 100 MHz
SHD benchmark	90.6% (LIF, 1024 hidden)
N-MNIST benchmark	99.2%
DVS Gesture benchmark	69.7%
GSC-12 benchmark	86.4%
FPGA validated	VU47P (16-core subset)
Paper	DOI 10.5281/zenodo.18727094

Loihi 2-class Production

Cores	1 (multi-core via NoC)
Neurons per core	1,024
Synapses per core	32,768
Neuron models	LIF, CUBA, Adaptive LIF
Spike format	Binary + Graded (8-bit payload)
Weight precision	16-bit signed
Membrane precision	16-bit signed
Compartments	4 per neuron (dendritic tree)
Delay support	0-63 timesteps per synapse
Learning rules	STDP, 3-factor (reward-modulated), dendritic
Noise injection	Per-neuron configurable
On-chip memory	128 KB SRAM (state + synaptic)
Network-on-Chip	Hierarchical packet-switched NoC
Clock frequency	62.5 MHz (FPGA)
Throughput	8,690 timesteps/second (sustained)
Spike latency	Sub-microsecond
Interface	AXI4-Lite + DMA
Target FPGA	Xilinx UltraScale+ (AWS F2)
LUT utilization	~85,000
BRAM utilization	~120 blocks
FPGA power	1.913 W (default), 0.991 W (5% activity)
FPGA LUTs	228,393 (VU47P)
Kria K26 (2-core)	26,431 LUTs (22.6%), 0.688W, ~97 MHz
SHD benchmark	84.5% (adLIF, 512 hidden)
N-MNIST benchmark	97.8%
SSC benchmark	72.1%
GSC benchmark	88.0%
MIT-BIH ECG benchmark	90.9%
ASIC projection	~9.3 mm², 19-38 mW at 28 nm
Paper	DOI 10.5281/zenodo.18728256

128-core SoC FPGA validated

Cores	128
Neurons per core	1,024
Total neurons	131,072
Total synapses	8,388,608
Neuron models	LIF, CUBA, Adaptive LIF, multi-compartment
Spike format	Binary + Graded (8-bit payload)
Weight precision	16-bit signed
Membrane precision	16-bit signed
Compartments	4 per neuron
Delay support	0-63 timesteps per synapse
Learning rules	STDP, 3-factor, dendritic, continual on-chip
Hardware virtualization	Time-multiplexed virtual cores
Memory hierarchy	L1 SRAM + L2 shared + L3 external DDR
Network-on-Chip	2D mesh, hierarchical routing
RISC-V management core	RV32I for configuration and monitoring
Clock frequency	62.5 MHz (FPGA)
Throughput	14,512 timesteps/second (8-core, sustained)
Interface	AXI4 (full) + PCIM for external memory
Target FPGA	Xilinx UltraScale+ (AWS F2)
Feature count	68 architectural features, all implemented
FPGA power	1.923 W (default)
FPGA LUTs	262,317 (VU47P)
AFI timing	WNS = 0.000 ns (timing met)
SHD benchmark	91.0%
SSC benchmark	76.4%
N-MNIST benchmark	99.1%
GSC-12 benchmark	88.0%
DVS Gesture benchmark	89.0%
Kria K26 (8-core)	53,420 LUTs (45.6%), 0.867W, ~58.5 MHz