Brain-inspired, from the silicon up
Our processors work the way neurons do, staying quiet until a signal changes and then responding in an instant, so a device can listen and decide for itself with no connection to the cloud.
Quiet until something happens
A microphone on a hillside hears wind and silence for most of the day, a conventional processor works through every one of those moments regardless, whereas our chip only does work when the sound changes, so the moment that matters gets its full attention.
Why spiking networks
Accuracy on the full Spiking Heidelberg Digits test set, run on our own hardware, against 90.9 percent published for Intel Loihi 2.
Events routed with none dropped, because a neuron is only updated when an event reaches it, so silence costs us nothing.
The hardware matches our reference simulator at every timestep, so a network that works in simulation works on the chip.
A network of 1.5 million connections loads from memory, so a new model is data as opposed to a new chip.
How we compare
The first column is from our own hardware. The other two are published figures, from Intel and from the research literature.
| Catalyst N4, on our FPGA | Intel Loihi 2, published | Research best, published | |
|---|---|---|---|
| Spiking Heidelberg Digits | 90.28 percent, full test set on chip | 90.9 percent | 96.41 percent, software |
| How the figure was obtained | Run on hardware, all 2,264 samples | Intel published figure | Published software result |
| Event loss | None across 18 million events | Not published | Not applicable |
| Power | Not measured, no board exists yet | Not compared | Not compared |
Signed off at 130 nm
The neuron update block, one part of a core, has completed physical signoff on an open 130 nm process. Nothing above that level has passed its checks yet, and we say so because the difference matters.
Inside N4-Edge*
Neuromorphic Compute Tiles
Brain-inspired cores that react the instant something changes.
On-Chip Model Memory
The model lives right beside the cores that run it.
RISC-V Management Subsystem
Its own processor brings the chip up and keeps it running.
Host Interface
A single link to the device it lives in.
Direct Sensor Interfaces
Sensors wire straight to the chip, with no host in between.
Always-On Power Domain
Stays awake so the rest of the chip does not have to.
Neuromorphic Compute Tiles
Brain-inspired cores that react the instant something changes.
On-Chip Model Memory
The model lives right beside the cores that run it.
RISC-V Management Subsystem
Its own processor brings the chip up and keeps it running.
Host Interface
A single link to the device it lives in.
Direct Sensor Interfaces
Sensors wire straight to the chip, with no host in between.
Always-On Power Domain
Stays awake so the rest of the chip does not have to.
From signal to decision
Sensor
A microphone, an accelerometer or a gas sensor produces a continuous signal, and most of it is quiet.
Events
The signal is turned into events, so only the moments where something changes carry forward.
Spiking network
The trained network sits on the cores, and only the neurons an event reaches are updated.
Decision
A result comes out of the chip, and the radio only wakes when there is something worth sending.
Inside the design
Blue blocks are built and validated on FPGA hardware. Outlined blocks are designed and not yet built.
Validated on an AMD Xilinx VU47P FPGA in July 2026, 48 cores at 62.5 MHz. N4-Edge is the smaller variant of the same core.Sensor interfaces
Host interface
Strict request and response
Model memory
Networks load from DDR in 0.94 s
Always-on domain
Neuromorphic fabric
48 cores on FPGA at 62.5 MHz, bit exact at every timestep
Neuron models
LIF, CUBA and adLIF, fixed point
Spike delivery
Weighted, event driven
RISC-V management core
CVA6, firmware drives the chip
Events out
Only when there is something worth sending
Telemetry
Every event counted, none dropped
Debug
On-chip learning
Specifications
Verified on hardware
- 48 cores at 62.5 MHz on an AMD Xilinx VU47P
- Full SHD test set run on chip, 90.28 percent, 2,044 of 2,264
- Bit exact against the reference model at every timestep
- Zero dropped events across more than 18 million routed
- Byte identical results across five successive builds
How far it scales
- 1,024 recurrent adLIF neurons with 20 readouts deployed
- 1.5 million connections in the deployed network
- 393,216 neuron fabric matched ideal maths on all 2,264 samples
- A model loads from memory in 0.94 seconds
- A RISC-V management core runs the chip from its own firmware
On the way to silicon
- Neuron update block through physical signoff at 130 nm
- 0.235 mm² of die, DRC clean, LVS matched, closing at 33 MHz
- N4-Edge target is 28 nm at 100 to 300 mW
- Power is a target, we have measured none of it yet
- First fabricated silicon planned for 2027
Specification in full
| Dimension | Catalyst N4-Edge, on our FPGA | Target for 28 nm silicon |
|---|---|---|
| Compute | 48 neuromorphic cores at 62.5 MHz, three neuron models in fixed point, LIF, CUBA and adLIF | 32 to 64 cores at 200 to 400 MHz |
| Neurons | 24,576 in the validated fabric, 393,216 in the largest build, which matched ideal maths on all 2,264 samples | 0.5 to 2 million, set by the SRAM on the die |
| Connections | 1.5 million resident, 32,768 per core | 64 to 256 million on the die |
| Neuron state | 17 bytes per neuron | same, and it sets the die split |
| Model store | DDR4, a 1.5 million connection model loads in 0.936 s | model memory on the die, switchable in the field |
| Models resident | 32 networks held at once and switched, byte identical per context | same |
| Management core | CVA6 RISC-V, firmware drives the chip | same |
| Host interface | PCIe and MMIO on AWS F2, AXI on the Kria K26 | SPI, QSPI and AXI, runs with no host |
| Sensor input | events injected by the host | AER in, event camera and acoustic front end |
| Determinism | bit exact against the reference model at every timestep, byte identical across five builds | carried forward by construction |
| Event integrity | zero drops across more than 18 million routed events | telemetry and counters kept as a product feature |
| Latency | 69 µs per timestep on an earlier measured configuration | under a millisecond from event to decision |
| Power | no device measurement exists, and no board exists yet | 100 to 300 mW running, under 10 mW in the wake domain |
| Process and package | not applicable, the design runs on an FPGA | 28 nm, package not yet chosen |
| Operating range | not defined | industrial range is the intent, nothing is qualified |
| Physical signoff | neuron update block at 130 nm on the IHP sg13g2 open PDK, 22,477 cells, 0.235 mm², DRC 0, LVS matched, 33.3 MHz | not started |
| CNN and DSP blocks | none, this is a spiking design | none planned |
| Toolchain | train in PyTorch, quantise to int16, check against the bit exact emulator, then place and program | same, plus adaptation on the device |
Four generations to N4
N1
Our first spiking processor, validated on FPGA hardware.
N2
Added programmable neuron models and learning on the chip.
N3
Split the design into tiles so it could scale.
N4
Built for the edge, and the design we are taking towards silicon. Everything on this page is about N4.
From trained model to running chip
Train in PyTorch
Spiking networks are trained with surrogate gradients, in a framework engineers already know.
Check in simulation
Our reference simulator matches the hardware exactly, so what works in simulation works on the device.
Run on hardware
The same network runs on FPGA hardware today, and N4-Edge is built to run it unchanged.
Put it in a product
N4-Edge silicon is planned for 2027, so today the same network runs on our FPGA and not yet in a product.
Sources
- Accuracy, event counts and timing come from our own runs on an AMD Xilinx VU47P FPGA in July 2026, on the full Spiking Heidelberg Digits test set.
- Power at 100 to 300 mW is a target for 28 nm. No power figure has been measured, and no board exists yet.
- Intel Loihi 2 at 90.9 percent and the research best at 96.41 percent are published figures, they are not our measurements.
- The N4-Edge image is an architectural visualisation of the design, it is not a photograph of a manufactured chip.
- The 130 nm area, DRC, LVS and frequency come from the signoff reports of an open 130 nm flow, and they cover the neuron update block only.
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